1. Field of the Invention
This invention relates in general to the field of pipelined microprocessor architecture, and more particularly to the prediction of conditional branch instruction outcomes.
2. Description of the Related Art
Computer instructions are typically stored in successive addressable locations within a memory. When processed by a Central Processing Unit (CPU), the instructions are fetched from consecutive memory locations and executed. Each time an instruction is fetched from memory, a program counter, or instruction pointer, within the CPU is incremented so that it contains the address of the next instruction in the sequence. This is the next sequential instruction pointer, or NSIP. Fetching of an instruction, incrementing of the program counter, and execution of the instruction continues linearly through memory until a program control instruction is encountered.
A program control instruction, when executed, changes the address in the program counter and causes the flow of control to be altered. In other words, program control instructions specify conditions for altering the contents of the program counter. The change in the value of the program counter as a result of the execution of a program control instruction causes a break in the sequence of instruction execution. This is an important feature in digital computers, as it provides control over the flow of program execution and a capability for branching to different portions of a program. Examples of program control instructions include Jump, Test and Jump conditionally, Call, and Return.
A Jump instruction causes the CPU to unconditionally change the contents of the program counter to a specific value, i.e., to the target address for the instruction where the program is to continue execution. A Test and Jump conditionally causes the CPU to test the contents of a status register, or possibly compare two values, and either continue sequential execution or jump to a new address, called the target address, based on the outcome of the test or comparison. A Call instruction causes the CPU to unconditionally jump to a new target address, but also saves the value of the program counter to allow the CPU to return to the program location it is leaving. A Return instruction causes the CPU to retrieve the value of the program counter that was saved by the last Call instruction, and return program flow back to the retrieved instruction address.
In early microprocessors, execution of program control instructions did not impose significant processing delays because such microprocessors were designed to execute only one instruction at a time. If the instruction being executed was a program control instruction, by the end of execution the microprocessor would know whether it should branch, and if it was supposed to branch, it would know the target address of the branch. Thus, whether the next instruction was sequential, or the result of a branch, it would be fetched and executed.
Modern microprocessors are not so simple. Rather, it is common for modern microprocessors to operate on several instructions at the same time, within different blocks or pipeline stages of the microprocessor. Hennessy and Patterson define pipelining as, xe2x80x9can implementation technique whereby multiple instructions are overlapped in execution.xe2x80x9d Computer Architecture: A Quantitative Approach, 2nd edition, by John L. Hennessy and David A. Patterson, Morgan Kaufmann Publishers, San Francisco, Calif., 1996. The authors go on to provide the following excellent illustration of pipelining:
A pipeline is like an assembly line. In an automobile assembly line, there are many steps, each contributing something to the construction of the car. Each step operates in parallel with the other steps, though on a different car. In a computer pipeline, each step in the pipeline completes a part of an instruction. Like the assembly line, different steps are completing different parts of the different instructions in parallel. Each of these steps is called a pipe stage or a pipe segment. The stages are connected one to the next to form a pipexe2x80x94instructions enter at one end, progress through the stages, and exit at the other end, just as cars would in an assembly line.
Thus, as instructions are fetched, they are introduced into one end of the pipeline. They proceed through pipeline stages within a microprocessor until they complete execution. In such pipelined microprocessors it is often not known whether a branch instruction will alter program flow until it reaches a late stage in the pipeline. However, by this time, the microprocessor has already fetched other instructions and is executing them in earlier stages of the pipeline. If a branch causes a change in program flow, all of the instructions in the pipeline that followed the branch must be thrown out. In addition, the instruction specified by the target address of the branch instruction must be fetched. Throwing out the intermediate instructions, and fetching the instruction at the target address creates processing delays in such microprocessors.
To alleviate this delay problem, many pipelined microprocessors use branch prediction mechanisms in an early stage of the pipeline that predict the outcome of branch instructions, and then fetch subsequent instructions according to the branch prediction.
A popular branch prediction scheme uses a branch history table (BHT), or prediction history table (PHT), to make predictions about conditional branch instruction outcomes. One simple BHT is an array of single bits. Each bit stores the last outcome of a branch instruction. For example, the bit stores a 1 if the branch was taken the last time it was executed and a 0 if the branch was not taken the last time it was executed.
The array is indexed by the address of the branch instruction. To make a prediction for a branch instruction, a branch predictor takes the address of the branch instruction and outputs the bit from the array entry selected by the address. Thus, the prediction for a given execution of a branch instruction is the outcome of the previous execution of the branch instruction. After the branch instruction executes (i.e., once the microprocessor resolves whether the branch is taken or not) the bit indexed by the branch instruction address is updated with the actual branch instruction outcome. A branch prediction mechanism such as a branch history table is commonly referred to as a dynamic branch prediction mechanism because it keeps a history of the outcome of branch instructions as a program executes and makes predictions based upon the history.
Many computer systems today have memory address ranges on the order of gigabytes. It is not practical for the BHT to be as large as the memory space of the system in which the microprocessor operates. Common BHT sizes are 1 KB to 4 KB. Therefore, only a portion of the address branch instruction is used to index into the BHT. Typically, the lower address bits are used as the index. Consequently, sometimes two or more branch instructions will index into the same location in the BHT. This phenomenon is commonly referred to as aliasing. This phenomenon occurs similarly in caches. However, most BHT""s do not have cache tags and sets. Therefore, the outcome of the newer branch will replace the outcome of the older branch. This may be detrimental if the older branch executes next, rather than the newer branch.
The aliasing phenomenon is also referred to as PHT interference, since the outcome of one branch is interfering with the subsequent prediction of another completely unrelated branch. See Eric Spangle, Robert S. Chappell, Mitch Alsup, Yale N. Patt, xe2x80x9cThe Agree Predictor: A Mechanism for Reducing Negative Branch History Interferencexe2x80x9d, Proceedings of the 24th International Symposium on Computer Architecture, Denver, June 1997, which is hereby incorporated by reference.
Spangle defines interference as xe2x80x9ca branch accessing a PHT entry that was previously updated by a different branch.xe2x80x9d He notes that interference may be positive, negative or neutral. A positive interference is one that causes a correct prediction that would otherwise have been a misprediction. A negative interference is one that causes a misprediction that would otherwise have been a correct prediction. A neutral interference is one that does not affect the correctness of the prediction. Spangle goes on to show that negative interference has a substantial impact on branch prediction accuracy overall.
Some solutions have attempted to reduce the number of interferences. One solution is to increase the size of the PHT. However, increasing the size of the PHT increases cost significantly because it requires a substantial additional amount of hardware.
Spangle proposes a solution to the interference problem that he refers to as xe2x80x9cagree prediction.xe2x80x9d Agree prediction, rather than attempting to reduce the number of interferences, converts negative interferences to positive or neutral interferences. This is accomplished by storing different information in the PHT than the outcome of the last branch instruction.
The agree prediction scheme relies on a biasing bit. The biasing bit indicates a prediction of the outcome of the branch. However, unlike the PHT entries, the value of the biasing bit is not updated with each execution of the branch instruction. The biasing bit remains the same over the course of program execution.
With agree prediction, the bit stored in the PHT predicts whether or not the branch outcome will be correctly predicted by the biasing bit, rather than predicting the branch outcome itself. Essentially, the agree predictor predicts whether the branch outcome will xe2x80x9cagreexe2x80x9d with the biasing bit""s prediction. Thus, each time a branch is resolved, the PHT is updated with an indication of whether the biasing bit agreed with the actual outcome.
U.S. Pat. No. 6,247,122, entitled Method and Apparatus for Performing Branch Prediction Combining Static and Dynamic Predictors, having the same assignee and inventors, and hereby incorporated by reference, describes a branch prediction method that employs a static prediction based on the test type in the opcode of a conditional branch instruction specifying a condition upon which the conditional branch instruction will be taken as a biasing bit for correlation with a single agree dynamic branch predictor.
Another branch prediction scheme that has been proposed is a hybrid branch prediction scheme. See Po-Yung Chang, Eric Hao and Yale N. Patt, xe2x80x9cAlternative Implementations of Hybrid Branch Predictorsxe2x80x9d, Proceedings of MICRO-28, 1995, which is hereby incorporated by reference, for a detailed discussion of hybrid branch predictors.
A hybrid branch prediction scheme employs multiple individual branch prediction schemes to make predictions about the outcome of a branch instruction in parallel, and attempts to select or predict which of the multiple schemes will make the correct prediction. A hybrid prediction scheme recognizes that different individual branch instructions within a given computer program may have different branch characteristics, and therefore different branch prediction schemes may be more accurate in predicting the branch outcome. For example, for some branch instructions, the best indication of any future outcome is the history of that particular branch instruction, commonly referred to as the local history. In contrast, for other branch instructions, the best indication of a future outcome is the history of other branch instructions within the program, commonly referred to as the global history. A hybrid prediction scheme attempts to capitalize on the variation in branch outcome characteristics by employing multiple individual branch prediction schemes, such as a local predictor and a global predictor, and selecting the appropriate individual prediction scheme on an instruction by instruction basis.
Chang describes a selection mechanism for selecting between two individual branch prediction schemes. The selection mechanism uses a Branch Predictor Selection Table (BPST) to select the individual branch prediction scheme. The BPST uses a BHT that is indexed as a function of the address of the branch instruction.
The Agree Predictor and hybrid predictor schemes alone provide improved performance. However, microprocessor pipeline depths continue to increase, resulting in more severe performance degradation when branches are mispredicted. This generates a demand for even greater branch prediction accuracy.
Therefore, what is needed is a branch prediction mechanism that combines the benefits of agree prediction and hybrid prediction to improve overall conditional branch instruction prediction.
To address the above-detailed deficiencies, it is an object of the present invention to provide an apparatus that provides improved branch prediction accuracy. Accordingly, in attainment of the aforementioned object, it is a feature of the present invention to provide a branch prediction mechanism. The branch prediction mechanism includes a static predictor, that makes a static prediction of whether a conditional branch instruction will be taken based on a test type of the conditional branch instruction, and a multiplexer, having a selection input, that selects one of two agree/disagree predictions. The mechanism also includes a selector, coupled to the multiplexer, that provides a selection signal to the selection input. The static prediction is correlated with the selected agree/disagree prediction to predict whether the conditional branch instruction will be taken.
In another aspect, it is a feature of the present invention to provide a method for updating a branch history table used in generating an agree/disagree signal for correlation with a static selection signal selecting one of two predictions of an outcome of a conditional branch instruction. The method includes receiving an indication of whether each of the two predictions correctly predicted the outcome and updating the branch history table only if the selected one of the two predictions incorrectly predicted the outcome and the non-selected prediction correctly predicted the outcome. The updating comprises storing an agree value in the branch history table if the branch history table generated disagree and storing a disagree value if the branch history table generated agree.
In yet another aspect, it is a feature of the present invention to provide a branch prediction mechanism in a microprocessor. The mechanism includes a static predictor, that generates a static prediction of an outcome of a conditional branch instruction based on a test type of the conditional branch instruction specifying a condition upon which the conditional branch instruction will be taken, and first and second branch predictors, that generate first and second agree/disagree predictions with the static prediction. The mechanism further includes a selector, that selects one of the first and second agree/disagree predictions and correlation logic, that correlates the static prediction and a selected one of the first and second agree/disagree predictions selected by the selector.
In yet another aspect, it is a feature of the present invention to provide an apparatus for selecting one of two predictions of an outcome of a conditional branch instruction made by a branch prediction mechanism of a microprocessor. The apparatus includes a history table, for storing a plurality of agree/disagree indications, that provides one of the plurality of agree/disagree indications on an output in response to an address of the conditional branch instruction. The apparatus also includes a correlator, coupled to the history table, for correlating a biasing bit signal generated by the branch prediction mechanism with the agree/disagree indication provided on the history table output to generate a selection signal for selecting one of the two predictions.
In yet another aspect, it is a feature of the present invention to provide an apparatus for selecting one of a plurality of predictions of an outcome of a conditional branch instruction. The apparatus includes a static predictor, that receives a test type of a conditional branch instruction for specifying a condition upon which the conditional branch instruction will be taken and to generate a selection signal and a multiplexer, that selects one of the plurality of predictions as a function of the selection signal.
In yet another aspect, it is a feature of the present invention to provide a method for selecting one of a plurality of predictions of an outcome of a conditional branch instruction by a branch prediction mechanism within a microprocessor. The method includes receiving a test type of a conditional branch instruction specifying a condition upon which the conditional branch instruction will be taken and selecting one of a plurality of predictions of an outcome of the conditional branch instruction based on the test type.
An advantage of the present invention is that it provides the improved prediction accuracy benefits of selectively employing local and global dynamic predictors and the constructive aliasing benefits of an Agree predictor, without having to incur the added cost of a biasing bit table, since the biasing bits are generated by the static predictor based on the conditional branch instruction test type. Another advantage of the present invention is that it enjoys the improved constructive aliasing benefits of the Agree predictor in the selector history table, without having to incur the added cost of a biasing bit table, since the biasing bits are generated by the static predictor based on the conditional branch instruction test type.